The present invention generally relates to a method for forming a fine pattern of a semiconductor device which has a pitch beyond a lithography process limit.
Due to the popularization of information media such as computers, semiconductor device technology has advanced rapidly. Semiconductor devices are required to operate at a high speed and to have a high storage capacity. As a result, manufacturing technology of semiconductor device is required to manufacture a memory device of high capacity with improved integration, reliability and characteristics for accessing data.
In order to improve integration of the device, photolithography technology has developed to form fine patterns. The photolithography technology includes an exposure technology using chemically amplified Deep Ultra Violet (DUV) light sources such as ArF (193 nm) and VUV (157 nm), and a technology developing photoresist materials suitable for the exposure light sources.
The processing speed of semiconductor devices depends on the line-width of patterns. For example, as the pattern line-width is decreased, the processing speed is increased to improve device performance. Therefore, it is important to control a critical dimension of the pattern line-width depending on the size of the semiconductor device.
Instead of developing a photoresist material, a method for forming a fine pattern having a reduced line-width using a double exposure and etching process has been applied in current semiconductor device manufacturing processes.
A conventional method for forming a fine pattern of a semiconductor device using a double exposure process is described as follows with reference to FIG. 1.
An underlying layer and a hard mask film are formed over a semiconductor substrate. A first lithography process is performed to form a first photoresist pattern 11 where a line-and-space pattern on a cell region is connected to a circuit pattern on a peripheral (peri) region in a bridge type configuration. A second lithography process is performed to form a second photoresist pattern 13 where a line-and-space pattern on a cell region is connected to a circuit pattern on a peri region in a bridge configuration, as shown in FIG. 1. The first photoresist pattern 11 is alternately arranged with the second photoresist pattern 13 in the cell region.
However, it is difficult to control the overlapping uniformity in the cell region {circle around (a)} by a resolution limit of the lithography equipment, and to form a pattern having a size less than a minimum pitch.